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19-3802; Rev 3; 6/08
16-Channel Buffered CMOS Logic-Level Translators
General Description
The MAX13101E/MAX13102E/MAX13103E/MAX13108E 16-bit bidirectional CMOS logic-level translators provide the level shifting necessary to allow data transfer in multivoltage systems. These devices are inherently bidirectional due to their design and do not require the use of a direction input. Externally applied voltages, VCC and VL, set the logic levels on either side of the devices. Logic signals present on the VL side of the device appear as a higher voltage logic signal on the VCC side of the device, and vice-versa. The MAX13101E/MAX13102E/MAX13103E feature an enable input (EN) that, when low, reduces the VCC and VL supply currents to less than 2A. The MAX13108E features a multiplexing input (MULT) that selects one byte between the two, thus allowing multiplexing of the signals. The MAX13101E/MAX13102E/MAX13103E/ MAX13108E have 15kV ESD protection on the I/O VCC side for greater protection in applications that route signals externally. Three different output configurations are available during shutdown, allowing the I/O on the VCC side or the VL side to be put in a high-impedance state or pulled to ground through an internal 6k resistor. The MAX13101E/MAX13102E/MAX13103E/MAX13108E accept V CC voltages from +1.65V to +5.5V and V L voltages from +1.2V to VCC, making them ideal for data transfer between low-voltage ASICs/PLDs and higher voltage systems. The MAX13101E/MAX13102E/ MAX13103E/MAX13108E are available in 36-bump WLP and 40-pin TQFN packages, and operate over the extended -40C to +85C temperature range.
Features
Wide Supply Voltage Range VCC Range of 1.65V to 5.5V VL Range of 1.2V to VCC ESD Protection on I/O VCC Lines 15kV Human Body Model Up to 20Mbps Throughput Low 0.03A Typical Quiescent Current WLP and TQFN Packages
MAX13101E/MAX13102E/MAX13103E/MAX13108E
Pin Configurations
TOP VIEW OF BOTTOM LEADS
I/O VCC10 I/O VCC11 I/O VCC5 I/O VCC6 I/O VCC7 I/O VCC8 I/O VCC9 GND I/O VCC12 22 GND 21 20 I/O VCC13 19 I/O VCC14 18 I/O VCC15 17 I/O VCC16 16 VCC 15 VL 14 I/O VL16 *EP 13 I/O VL15 12 I/O VL14 11 I/O VL13 2 I/O VL5 3 I/O VL6 4 I/O VL7 5 I/O VL8 6 I/O VL9 7 I/O VL10 8 I/O VL11 9 I/O VL12 10 EN
30 I/O VCC4 I/O VCC3 I/O VCC2 I/O VCC1 VCC VL I/O VL1 I/O VL2 I/O VL3 I/O VL4 31 32 33 34 35 36 37 38 39 40
29
28
27
26
25
24
23
MAX13101E MAX13102E MAX13103E
+
1 GND
Applications
CMOS Logic-Level Translation Portable Equipment Cell Phones PDAs Digital Still Cameras Smart Phones
*EXPOSED PAD CONNECTED TO GROUND
TQFN
Pin Configurations continued at end of data sheet. Typical Operating Circuit appears at end of data sheet.
Ordering Information/Selector Guide
PART MAX13101EEWX+* MAX13101EETL+ PIN-PACKAGE 36 WLP** 3.06mm x 3.06mm DATA RATE (Mbps) 20 I/O VL STATE DURING SHUTDOWN High impedance I/O VCC STATE DURING SHUTDOWN 6k to GND 6k to GND MULTIPLEXER FEATURE No No
40 TQFN-EP*** 20 High impedance 5mm x 5mm x 0.8mm Note: All devices are specified over the -40C to +85C operating temperature range. +Denotes a lead-free/RoHS-compliant package. *Future product--contact factory for availability. **WLP bumps are in a 6 x 6 array. ***EP = Exposed pad.
Ordering Information/Selector Guide continued at end of data sheet.
________________________________________________________________ Maxim Integrated Products 1
For pricing, delivery, and ordering information, please contact Maxim Direct at 1-888-629-4642, or visit Maxim's website at www.maxim-ic.com.
16-Channel Buffered CMOS Logic-Level Translators MAX13101E/MAX13102E/MAX13103E/MAX13108E
ABSOLUTE MAXIMUM RATINGS
(All voltages referenced to GND.) VCC ...........................................................................-0.3V to +6V VL...........................................................................................-0.3V to +6V I/O VCC_......................................................-0.3V to (VCC + 0.3V) I/O VL_ .....................................................................-0.3V to (VL + 0.3V) EN, MULT .................................................................-0.3V to +6V Short-Circuit Duration I/O VL_, I/O VCC_ to GND .......Continuous Continuous Power Dissipation (TA = +70C) 36-Bump WLP (derate 17.0mW/C above +70C).....1361mW 40-Pin TQFN (derate 35.7mW/C above +70C) .......2857mW Operating Temperature Range ...........................-40C to +85C Maximum Junction Temperature .....................................+150C Storage Temperature Range ............................-65C to +150C Lead Temperature (soldering, 10s) .................................+300C
Stresses beyond those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.
ELECTRICAL CHARACTERISTICS
(VCC = +1.65V to +5.5V, VL = +1.2V to VCC, EN = VL (MAX13101E/MAX13102E/MAX13103E), MULT = VL or GND (MAX13108E), TA = TMIN to TMAX, unless otherwise noted. Typical values are at VCC = +1.65V, VL = +1.2V, TA = +25C.) (Notes 1, 2)
PARAMETER POWER SUPPLIES VL Supply Range VCC Supply Range Supply Current from VCC VL VCC IQVCC I/O VCC_ = GND, I/O VL _ = GND or I/O VCC_ = VCC, I/O VL _ = VL, EN = VL, MULT = GND or VL I/O VCC_ = GND, I/O VL _ = GND or I/O VCC_ = VCC, I/O VL _ = VL, EN = VL, MULT = GND or VL TA = +25C, EN = GND, I/O VCC_ = GND, I/O VL _ = GND, MAX13101E/MAX13102E/MAX13103E TA = +25C, EN = GND, I/O VCC_ = GND, I/O VL _ = GND, MAX13101E/MAX13102E/MAX13103E TA = +25C, EN = GND, MAX13102E/MAX13103E I/O VCC_ Tri-State Output Leakage Current TA = +25C, MULT = GND (I/O VCC1 - I/O VCC 8) or MULT = VL (I/O VCC 9 - I/O VCC 16) MAX13108E TA = +25C, EN = GND, MAX13101E/ MAX13103E I/O VL _ Tri-State Output Leakage Current TA = +25C, MULT = GND (I/O VL1 - I/O VL8) or MULT = VL (I/OVL9 - I/O VL16) MAX13108E EN = GND, MAX13102E 4 1.2 1.65 0.03 VCC 5.50 10 V V A SYMBOL CONDITIONS MIN TYP MAX UNITS
Supply Current from VL
IQVL
0.03
20
A
VCC Shutdown Supply Current
ISHDN-VCC
0.03
1
A
VL Shutdown Supply Current
ISHDN-VL
0.03
2
A
0.02
1 A
0.02
1
0.02
1 A
0.02
1
I/O VL _ Pulldown Resistance During Shutdown
10
k
2
_______________________________________________________________________________________
16-Channel Buffered CMOS Logic-Level Translators
ELECTRICAL CHARACTERISTICS (continued)
(VCC = +1.65V to +5.5V, VL = +1.2V to VCC, EN = VL (MAX13101E/MAX13102E/MAX13103E), MULT = VL or GND (MAX13108E), TA = TMIN to TMAX, unless otherwise noted. Typical values are at VCC = +1.65V, VL = +1.2V, TA = +25C.) (Notes 1, 2)
PARAMETER I/O VCC_ Pulldown Resistance During Shutdown EN or MULT Input Leakage Current LOGIC-LEVEL THRESHOLDS I/O VL _ Input-Voltage High Threshold I/O VL _ Input-Voltage Low Threshold I/O VCC_ Input-Voltage High Threshold I/O VCC_ Input-Voltage Low Threshold EN, MULT Input-Voltage High Threshold EN, MULT Input-Voltage Low Threshold I/O VL _ Output-Voltage High I/O VL _ Output-Voltage Low I/O VCC_ Output-Voltage High I/O VCC_ Output-Voltage Low VIHL VILL VIHC VILC VIH-SHDN VIL-SHDN VOHL VOLL VOHC VOLC 0.4 I/O VL _ source current = 20A, I/O VCC_ VIHC VL - 0.4 I/O VL _ sink current = 20A, I/O VCC_ VILC I/O VCC_ source current = 20A, I/O VL _ VIHL VCC - 0.4 I/O VCC_ sink current = 20A, I/O VL _ VILL I/O VCC side I/O VL side VL = 1.2V, VCC = 1.65V VL = 1.2V, VCC = 1.65V VL = 5V, VCC = 5V VL = 1.2V, VCC = 1.65V VL = 5V, VCC = 5V VL = 1.2V, VCC = 1.65V VL = 5V, VCC = 5V VL = 1.2V, VCC = 1.65V VL = 5V, VCC = 5V Human Body Model VCC / 2 VL / 2 20 60 5 15 5 30 5 20 7 15 0.4 0.4 1/3 x VCC VL - 0.4 1/3 x VL 2/3 x VCC 2/3 x VL V V V V V V V V V V SYMBOL CONDITIONS EN = GND, MAX13101E TA = +25C MIN 4 TYP MAX 10 1 UNITS k A
MAX13101E/MAX13102E/MAX13103E/MAX13108E
RISE/FALL-TIME ACCELERATOR STAGE Transition-Detect Threshold Accelerator Pulse Duration I/O VL _ Output-Accelerator Sink Impedance I/O VCC_ Output-Accelerator Sink Impedance I/O VL _ Output-Accelerator Source Impedance I/O VCC_ Output-Accelerator Source Impedance ESD PROTECTION I/O VCC_ kV V ns
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3
16-Channel Buffered CMOS Logic-Level Translators MAX13101E/MAX13102E/MAX13103E/MAX13108E
TIMING CHARACTERISTICS
(VCC = +1.65V to +5.5V, VL = +1.2V to VCC, EN = VL (MAX13101E/MAX13102E/MAX13103E), MULT = VL or GND (MAX13108E), TA = TMIN to TMAX, unless otherwise noted. Typical values are at VCC = +1.65V, VL = +1.2V, TA = +25C.) (Notes 1, 2)
PARAMETER I/O VL _ Rise Time I/O VL _ Fall Time I/O VCC_ Rise Time I/O VCC_ Fall Time Propagation Delay (Driving I/O VL _) Propagation Delay (Driving I/O VCC_) Channel-to-Channel Skew Part-to-Part Skew Propagation Delay from I/O VL _ to I/O VCC_ After EN Propagation Delay from I/O VCC_ to I/O VL _ After EN Maximum Data Rate SYMBOL tRVL tFVL tRVCC tFVCC tPVL-VCC tPVCC-VL tSKEW tPPSKEW tEN-VCC tEN-VL CONDITIONS RS = 50, CI/OVL_ = 15pF, tRISE 3ns, (Figures 2a, 2b) RS = 50, CI/OVL_ = 15pF, tFALL 3ns, (Figures 2a, 2b) RS = 50, CI/OVCC_ = 50pF, tRISE 3ns, (Figures 1a, 1b) RS = 50, CI/OVCC_ = 50pF, tFALL 3ns, (Figures 1a, 1b) RS = 50, CI/OVCC_ = 50pF, tRISE 3ns, (Figures 1a, 1b) RS = 50, CI/OVL_ = 15pF, tRISE 3ns, (Figures 2a, 2b) RS = 50, CI/OVCC_ = 50pF, CI/OVL_ = 15pF, tRISE 3ns RS = 50, CI/OVCC_ = 50pF, CI/OVL_ = 15pF, tRISE 3ns, TA = +20C (Notes 3, 4) CI/OVCC_ = 50pF (Figure 3) CI/OVL_ = 15pF (Figure 4) RSOURCE = 50, CI/OVCC_ = 50pF, CI/OVL_ = 15pF, tRISE 3ns 20 MIN TYP MAX 15 15 15 15 20 20 5 10 1 1 UNITS ns ns ns ns ns ns ns ns s s Mbps
Note 1: All units are 100% production tested at TA = +25C. Limits over the operating temperature range are guaranteed by design and not production tested. Note 2: For normal operation, ensure that VL < (VCC + 0.3V). During power-up, VL > (VCC + 0.3V) does not damage the device. Note 3: VCC from device 1 must equal VCC of device 2. VL from device 1 must equal VL of device 2. Note 4: Guaranteed by design, not production tested.
4
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16-Channel Buffered CMOS Logic-Level Translators
Test Circuits/Timing Diagrams
tRISE/FALL 3ns
MAX13101E/MAX13102E/MAX13103E/MAX13108E
VL
MAX13101E MAX13102E MAX13103E MAX13108E
EN/(MULT) 6k I/O VL_ 6k I/O VCC_
I/O VL_
VCC
90% 50% 10% tPLH tPHL I/O VCC_ 50%
SOURCE
RS
CI/OVCC_
90% 50% 10%
90%
10%
ALL UNUSED I/O VCC_ AND I/O VL_ CONNECTED TO GND ( ) ARE FOR THE MAX13108E
tPVL-VCC = tPHL or tPLH
tFVCC
tRVCC
Figure 1a. Driving I/O VL_
Figure 1b. Timing for Driving I/O VL_
tRISE/FALL 3ns
VL EN/(MULT)
MAX13101E MAX13102E MAX13103E MAX13108E
6k RS I/O VL_ CI/OVL_ 6k I/O VCC_
VCC
I/O VCC_ 90% 50% 10% tPLH tPHL SOURCE I/O VL_ 90% 50% 10% 10% 50%
90%
ALL UNUSED I/O VCC_ AND I/O VL_ CONNECTED TO GND ( ) ARE FOR THE MAX13108E tPVCC-VL = tPHL or tPLH tFVL tRVL
Figure 2a. Driving I/O VCC_
Figure 2b. Timing for Driving I/O VCC_
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5
16-Channel Buffered CMOS Logic-Level Translators MAX13101E/MAX13102E/MAX13103E/MAX13108E
Test Circuits/Timing Diagrams (continued)
MAX13101E MAX13102E MAX13103E MAX13108E
EN/(MULT) SOURCE I/O VL_ VL 6k CI/OVCC 6k I/O VCC_
VL EN/(MULT) tEN-VCC 0 VL I/O VL_ 0 100k I/O VCC_ VCC
2
VCC
( ) ARE FOR THE MAX13108E
Figure 3. Propagation Delay from I/O VL_ to I/O VCC_ After EN
MAX13101E MAX13102E MAX13103E MAX13108E
EN/(MULT) SOURCE 6k I/O VL_ 6k 100k CI/OVL I/O VCC_ VCC
VL EN/(MULT) tEN-VL 0 VCC I/O VCC_ 0 VL
2
VL 0
I/O VL_
( ) ARE FOR THE MAX13108E
Figure 4. Propagation Delay from I/O VCC_ to I/O VL_ After EN
6
_______________________________________________________________________________________
16-Channel Buffered CMOS Logic-Level Translators
Typical Operating Characteristics
(VCC = 3.3V, VL = 1.8V, data rate = 20Mbps, TA = +25C, unless otherwise noted.)
VL SUPPLY CURRENT vs. VCC SUPPLY VOLTAGE (DRIVING I/0 VL_, VL = 1.8V)
MAX13101-3/8E toc01
MAX13101E/MAX13102E/MAX13103E/MAX13108E
VL SUPPLY CURRENT vs. VL SUPPLY VOLTAGE (DRIVING I/0 VCC_, VCC = 5.5V)
DRIVING ONE I/O VCC VL SUPPLY CURRENT (A) 2000 FIGURE 2a CI/OVL_ = 15pF 1500
. MAX13101-3/8E toc02
120 DRIVING ONE I/O VL 100 VL SUPPLY CURRENT (A) 80 60 40 20 0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 VCC SUPPLY VOLTAGE (V) 5.0 FIGURE 1a CI/OVCC_ = 15pF
2500
1000
500
0 5.5 1.5 2.0 2.5 3.0 3.5 4.0 4.5 VL SUPPLY VOLTAGE (V) 5.0 5.5
VCC SUPPLY CURRENT vs. VCC SUPPLY VOLTAGE (DRIVING I/0 VL_, VL = 1.8V)
MAX13101-3/8 toc03
VCC SUPPLY CURRENT vs. VL SUPPLY VOLTAGE (DRIVING I/0 VCC_, VCC = 5.5V)
DRIVING ONE I/O VCC 7000 FIGURE 2a VCC SUPPLY CURRENT (A) 6000 5000 4000 3000 2000 1000 0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 VL SUPPLY VOLTAGE (V) 5.0 5.5 CI/OVL_ = 15pF
MAX13101-3/8 toc04
8000 DRIVING ONE I/O VL 7000 FIGURE 1a VCC SUPPLY CURRENT (A) 6000 5000 4000 3000 2000 1000 0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 VCC SUPPLY VOLTAGE (V) 5.0 CI/OVCC_ = 15pF
8000
5.5
VL SUPPLY CURRENT vs. TEMPERATURE (DRIVING I/O VCC_)
MAX13101-3/8E toc05
VCC SUPPLY CURRENT vs. TEMPERATURE (DRIVING I/O VCC_)
DRIVING ONE I/O VCC 2500 VCC SUPPLY CURRENT (A) 2000 1500 1000 500 0 FIGURE 2a CI/OVL_ = 15pF
MAX13101-3/8 toc06
800 700 VL SUPPLY CURRENT (A) 600 500 400 300 200 100 0 -40 -15 10 35 TEMPERATURE (C) 60 DRIVING ONE I/O VCC FIGURE 2a CI/OVL_ = 15pF
3000
85
-40
-15
10 35 TEMPERATURE (C)
60
85
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7
16-Channel Buffered CMOS Logic-Level Translators MAX13101E/MAX13102E/MAX13103E/MAX13108E
Typical Operating Characteristics (continued)
(VCC = 3.3V, VL = 1.8V, data rate = 20Mbps, TA = +25C, unless otherwise noted.)
VL SUPPLY CURRENT vs. CAPACITIVE LOAD ON I/O VL_ (DRIVING I/O VCC_)
MAX13101-3/8E toc07
VCC SUPPLY CURRENT vs. CAPACITIVE LOAD ON I/O VCC_ (DRIVING I/O VL_)
MAX13101-3/8E toc08
RISE/FALL TIME vs. CAPACITIVE LOAD ON I/O VCC_ (DRIVING I/O VL_)
FIGURES 1a, 1b 3 RISE/FALL TIME (ns) tRVCC
MAX13101-3/8E toc09
1200 DRIVING ONE I/O VCC 1000 VL SUPPLY CURRENT (A) 800 600 400 200 0 10 20 30 40 CAPACITIVE LOAD (pF) FIGURE 2a
5000 DRIVING ONE I/O VL VCC SUPPLY CURRENT (A) 4000 FIGURE 1a
4
3000
2
tFVCC
2000
1000
1
0 50 10 20 30 40 CAPACITIVE LOAD (pF) 50
0 10 20 30 40 CAPACITIVE LOAD (pF) 50
RISE/FALL TIME vs. CAPACITIVE LOAD ON I/O VL_ (DRIVING I/O VCC_)
MAX13101-3/8E toc10
PROPAGATION DELAY vs. CAPACITIVE LOAD ON I/O VCC_ (DRIVING I/O VL_)
FIGURES 1a, 1b 8 PROPAGATION DELAY (ns) tPLH
MAX13101-3/8E toc11
7 6 RISE/FALL TIME (ns) 5 4 3 2 1 0 10 20 30 40 CAPACITIVE LOAD (pF) tFVL tRVL FIGURES 2a, 2b
10
6
4 tPHL 2
0 50 10 20 30 40 CAPACITIVE LOAD (pF) 50
8
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16-Channel Buffered CMOS Logic-Level Translators
Typical Operating Characteristics (continued)
(VCC = 3.3V, VL = 1.8V, data rate = 20Mbps, TA = +25C, unless otherwise noted.)
PROPAGATION DELAY vs. CAPACITIVE LOAD ON I/O VL_ (DRIVING I/O VCC_)
FIGURES 2a, 2b 4 PROPAGATION DELAY (ns) tPLH GND 2 I/0 VCC_ 2V/div GND 0 10 20 30 40 CAPACITIVE LOAD (pF) 50 10ns/div tPHL
MAX13101-3/8E toc12
MAX13101E/MAX13102E/MAX13103E/MAX13108E
RAIL-TO-RAIL DRIVING (DRIVING I/O VL)
CI/OVCC_= 50pF
5
MAX13101E-3/8E toc13
I/0 VL_ 1V/div
3
1
Pin Description--MAX13101E/MAX13102E/MAX13103E
PIN TQFN 1, 21, 30 2 3 4 5 6 7 8 9 10 11 12 13 14 15, 36 16, 35 17 18 WLP D6 C2 A3 B3 C3 A4 B4 C4 A5 C6 B5 C5 A6 B6 A1 F1 E6 F6 NAME GND I/O VL5 I/O VL6 I/O VL7 I/O VL8 I/O VL9 I/O VL10 I/O VL11 I/O VL12 EN I/O VL13 I/O VL14 I/O VL15 I/O VL16 VL VCC Ground Input/Output 5. Referenced to VL. Input/Output 6. Referenced to VL. Input/Output 7. Referenced to VL. Input/Output 8. Referenced to VL. Input/Output 9. Referenced to VL. Input/Output 10. Referenced to VL. Input/Output 11. Referenced to VL. Input/Output 12. Referenced to VL. Global Enable Input. Pull EN low for shutdown. Drive EN to VCC or VL for normal operation. Input/Output 13. Referenced to VL. Input/Output 14. Referenced to VL. Input/Output 15. Referenced to VL. Input/Output 16. Referenced to VL. Logic Supply Voltage, +1.2V VL VCC. Bypass VL to GND with a 0.1F capacitor. VCC Supply Voltage, +1.65V VCC +5.5V. Bypass VCC to GND with a 0.1F capacitor. For full ESD protection, connect a 1.0F capacitor from VCC to GND, located as close to the VCC input as possible. FUNCTION
I/O VCC16 Input/Output 16. Referenced to VCC. I/O VCC15 Input/Output 15. Referenced to VCC.
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9
16-Channel Buffered CMOS Logic-Level Translators MAX13101E/MAX13102E/MAX13103E/MAX13108E
Pin Description--MAX13101E/MAX13102E/MAX13103E (continued)
PIN TQFN 19 20 22 23 24 25 26 27 28 29 31 32 33 34 37 38 39 40 -- WLP D5 E5 F5 D4 E4 F4 D3 E3 F3 D2 E2 F2 D1 E1 B1 C1 A2 B2 -- NAME I/O VCC14 Input/Output 14. Referenced to VCC. I/O VCC13 Input/Output 13. Referenced to VCC. I/O VCC12 Input/Output 12. Referenced to VCC. I/O VCC11 Input/Output 11. Referenced to VCC. I/O VCC10 Input/Output 10. Referenced to VCC. I/O VCC9 I/O VCC8 I/O VCC7 I/O VCC6 I/O VCC5 I/O VCC4 I/O VCC3 I/O VCC2 I/O VCC1 I/O VL1 I/O VL2 I/O VL3 I/O VL4 EP Input/Output 9. Referenced to VCC. Input/Output 8. Referenced to VCC. Input/Output 7. Referenced to VCC. Input/Output 6. Referenced to VCC. Input/Output 5. Referenced to VCC. Input/Output 4. Referenced to VCC. Input/Output 3. Referenced to VCC. Input/Output 2. Referenced to VCC. Input/Output 1. Referenced to VCC. Input/Output 1. Referenced to VL. Input/Output 2. Referenced to VL. Input/Output 3. Referenced to VL. Input/Output 4. Referenced to VL. Exposed Pad. Connect EP to GND. FUNCTION
Pin Description--MAX13108E
PIN TQFN 1, 21, 30 2 3 4 5 6 7 8 9 WLP D6 C2 A3 B3 C3 A4 B4 C4 A5 NAME GND I/O VL5 I/O VL6 I/O VL7 I/O VL8 I/O VL9 I/O VL10 I/O VL11 I/O VL12 Ground Input/Output 5. Referenced to VL. Input/Output 6. Referenced to VL. Input/Output 7. Referenced to VL. Input/Output 8. Referenced to VL. Input/Output 9. Referenced to VL. Input/Output 10. Referenced to VL. Input/Output 11. Referenced to VL. Input/Output 12. Referenced to VL. FUNCTION
10
______________________________________________________________________________________
16-Channel Buffered CMOS Logic-Level Translators
Pin Description--MAX13108E (continued)
PIN TQFN 10 11 12 13 14 15, 36 16, 35 17 18 19 20 22 23 24 25 26 27 28 29 31 32 33 34 37 38 39 40 -- WLP C6 B5 C5 A6 B6 A1 F1 E6 F6 D5 E5 F5 D4 E4 F4 D3 E3 F3 D2 E2 F2 D1 E1 B1 C1 A2 B2 -- NAME FUNCTION Multiplexing Input. Drive MULT low to enable channels 9 to 16. Driving MULT low puts channels 1 to 8 into tri-state. Drive MULT to VCC or VL to enable channels 1 to 8. Driving MULT to VCC or VL puts channels 9 to 16 into tri-state. Input/Output 13. Referenced to VL. Input/Output 14. Referenced to VL. Input/Output 15. Referenced to VL. Input/Output 16. Referenced to VL. Logic Supply Voltage, +1.2V VL VCC. Bypass VL to GND with a 0.1F capacitor. VCC Supply Voltage, +1.65V VCC +5.5V. Bypass VCC to GND with a 0.1F capacitor. For full ESD protection, connect a 1.0F capacitor from VCC to GND, located as close to the VCC input as possible.
MAX13101E/MAX13102E/MAX13103E/MAX13108E
MULT I/O VL13 I/O VL14 I/O VL15 I/O VL16 VL VCC
I/O VCC16 Input/Output 16. Referenced to VCC. I/O VCC15 Input/Output 15. Referenced to VCC. I/O VCC14 Input/Output 14. Referenced to VCC. I/O VCC13 Input/Output 13. Referenced to VCC. I/O VCC12 Input/Output 12. Referenced to VCC. I/O VCC11 Input/Output 11. Referenced to VCC. I/O VCC10 Input/Output 10. Referenced to VCC. I/O VCC9 I/O VCC8 I/O VCC7 I/O VCC6 I/O VCC5 I/O VCC4 I/O VCC3 I/O VCC2 I/O VCC1 I/O VL1 I/O VL2 I/O VL3 I/O VL4 EP Input/Output 9. Referenced to VCC. Input/Output 8. Referenced to VCC. Input/Output 7. Referenced to VCC. Input/Output 6. Referenced to VCC. Input/Output 5. Referenced to VCC. Input/Output 4. Referenced to VCC. Input/Output 3. Referenced to VCC. Input/Output 2. Referenced to VCC. Input/Output 1. Referenced to VCC. Input/Output 1. Referenced to VL. Input/Output 2. Referenced to VL. Input/Output 3. Referenced to VL. Input/Output 4. Referenced to VL. Exposed Pad. Connect EP to GND.
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11
16-Channel Buffered CMOS Logic-Level Translators MAX13101E/MAX13102E/MAX13103E/MAX13108E
Functional Diagrams
VL VCC
VL VCC
MULT
EN
MAX13101E MAX13102E MAX13103E
I/O VCC1
MAX13108E
I/O VL1 I/O VCC1
I/O VL1
I/O VL2
I/O VCC2
I/O VL2
I/O VCC2
I/O VL3 I/O VCC3
I/O VL3
I/O VCC3
I/O VL4 I/O VCC4
I/O VL4
I/O VCC4
I/O VL5 I/O VCC5
I/O VL5
I/O VCC5
I/O VL6 I/O VCC6
I/O VL6
I/O VCC6
I/O VL7 I/O VCC7
I/O VL7
I/O VCC7
I/O VL8
I/O VCC8
I/O VL8
I/O VCC8
I/O VL9
I/O VCC9
I/O VL9 I/O VCC9
I/O VL10
I/O VCC10
I/O VL10 I/O VCC10
I/O VL11
I/O VCC11
I/O VL11 I/O VCC11
I/O VL12
I/O VCC12
I/O VL12 I/O VCC12
I/O VL13
I/O VCC13
I/O VL13
I/O VCC13
I/O VL14
I/O VCC14
I/O VL14
I/O VCC14
I/O VL15
I/O VCC15
I/O VL15
I/O VCC15
I/O VL16 GND
I/O VCC16
I/O VL16 GND
I/O VCC16
12
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16-Channel Buffered CMOS Logic-Level Translators
Detailed Description
The MAX13101E/MAX13102E/MAX13103E/MAX13108E logic-level translators provide the level shifting necessary to allow data transfer in a multivoltage system. Externally applied voltages, VCC and VL, set the logic levels on either side of the device. Logic signals present on the VL side of the device appear as a higher voltage logic signal on the VCC side of the device, and vice-versa. The MAX13101E/MAX13102E/MAX13103E/ MAX13108E are bidirectional level translators allowing data translation in either direction (V L V CC ) on any single data line. The MAX13101E/MAX13102E/ MAX13103E/MAX13108E accept VL from +1.2V to VCC. All devices have a VCC range from +1.65V to +5.5V, making them ideal for data transfer between low-voltage ASICs/PLDs and higher voltage systems. The MAX13101E/MAX13102E/MAX13103E feature an output enable mode that reduces VCC supply current to less than 1A, and VL supply current to less than 2A when in shutdown. The MAX13108E features a multiplexing input that selects one byte between the two, thus allowing multiplexing of the signals. The MAX13101E/MAX13102E/MAX13103E/MAX13108E have 15kV ESD protection on the I/O VCC side for greater protection in applications that route signals externally. The MAX13101E/MAX13102E/MAX13103E/ MAX13108E operate at a guaranteed data rate of 20Mbps. The maximum data rate depends heavily on the load capacitance (see the Typical Operating Characteristics) and the output impedance of the external driver.
MAX13101E/MAX13102E/MAX13103E/MAX13108E
VBATT VCC SUPPLY DISABLE +1.2V TO +5.5V
VCC
VL
RDSON < 50
MAX13101E MAX13102E MAX13103E MAX13108E
I/O VCC1 I/O VL1
I/O VCC16 GND
I/O VL16
Figure 5. Recommended Circuit for Powering Down VCC
the bidirectional nature, both input stages become active during the one-shot pulse. This can lead to some current feeding into the external source that is driving the translator. However, this behavior helps to speed up the transition on the driven side. For proper full-speed operation, the output current of a device that drives the inputs of the MAX13101E/ MAX13102E/MAX13103E/MAX13108E should meet the following requirement: i > 108 x V x (C + 10pF) where, i is the driver output current, V is the logic-supply voltage (i.e., VL or VCC) and C is the parasitic capacitance of the signal line.
Power-Supply Sequencing
For proper operation, ensure that +1.65V VCC +5.5V, +1.2V VL +5.5V, and VL VCC. During power-up sequencing, VL VCC does not damage the device. When VCC is disconnected and VL is powering up, up to 10mA of current can be sourced to each load on the VL side, yet the device does not latch up. To guarantee that no excess leakage current flows and that the device does not interfere with the I/O on the VL side, VCC should be connected to GND with a max 50 resistor when the VCC supply is not present (Figure 5).
Enable Output Mode (EN)
The MAX13101E/MAX13102E/MAX13103E feature an enable input (EN) that, when driven low, places the device into shutdown mode. During shutdown, the MAX13101E I/O VCC_ ports are pulled down to ground with internal 6k resistors and the I/O VL _ ports enter tri-state. MAX13102E I/O VCC_ lines enter tri-state and the I/OVL _ lines are pulled down to ground with internal 6k resistors. All I/O VCC_ and I/O VL _ lines on the MAX13103E enter tri-state while the device is in shutdown mode. During shutdown, the VCC supply current reduces to less than 1A, and the VL supply current reduces to less than 2A. To guarantee minimum shutdown supply current, all I/O VL _ need to be driven to GND or V L , or pulled to GND or V L through 100k resistors. All I/O VCC_ need to be driven to GND or VCC, or pulled to GND or VCC through 100k resistors. Drive EN to logic-high (VL or VCC) for normal operation.
13
Input Driver Requirements
The MAX13101E/MAX13102E/MAX13103E/MAX13108E architecture is based on a one-shot accelerator output stage (Figure 6). Accelerator output stages are always in tri-state except when there is a transition on any of the translators on the input side, either I/O V L _ or I/O V CC _. Then a short pulse is generated, during which the accelerator output stages become active and charge/discharge the capacitances at the I/Os. Due to
______________________________________________________________________________________
16-Channel Buffered CMOS Logic-Level Translators MAX13101E/MAX13102E/MAX13103E/MAX13108E
Multiplexing Input (MULT)
VL VCC
RISE-TIME ACCELERATOR I/O VL_ I/O VCC_
FALL-TIME ACCELERATOR
The MAX13108E features a multiplexing input (MULT) that enables 8 of the 16 channels and places the remaining 8 into tri-state. Figure 7 depicts a typical multiplexing configuration using the MAX13108E. Drive MULT high to enable I/O VCC1 through I/O VCC8 and I/O V L 1 through I/O V L 8. Driving MULT high sets I/O VCC9 through I/O VCC16 and I/O VL9 through I/O VL16 into tri-state. Drive MULT low to enable I/O VCC9 through I/O V CC 16 and I/O V L 9 through I/O V L 16. Driving MULT low sets I/O VCC1 through I/O VCC8 and I/O VL1 through I/O VL8 into tri-state.
15kV ESD Protection
As with all Maxim devices, ESD-protection structures are incorporated on all pins to protect against electrostatic discharges encountered during handling and assembly. The I/O VCC_ lines have extra protection against static discharge. Maxim's engineers have developed state-ofthe-art structures to protect these pins against ESD of 15kV without damage. The ESD structures withstand high ESD in all states: normal operation, tri-state output mode, and powered down. After an ESD event, Maxim's E versions keep working without latchup, whereas competing products can latch and must be powered down to remove the latchup condition. ESD protection can be tested in various ways. The I/O V CC _ lines of the MAX13101E/ MAX13102E/ MAX13103E/MAX13108E are characterized for protection to 15kV using the Human Body Model.
RISE-TIME ACCELERATOR
FALL-TIME ACCELERATOR
MAX13101E MAX13102E MAX13103E MAX13108E
Figure 6. Simplified Diagram (1 I/O Line)
I/O VL1 I/O VL2 I/O VL3 PORT A I/O VL4 I/O VL5 I/O VL6 I/O VL7 I/O VL8
MULT
I/O VCC1 I/O VCC2 I/O VCC3 I/O VCC4 I/O VCC5 I/O VCC6 I/O VCC7 I/O VCC8
MAX13108E
I/O VL9 I/O VL10 I/O VL11 PORT B I/O VL12 I/O VL13 I/O VL14 I/O VL15 I/O VL16 I/O VCC9 I/O VCC10 I/O VCC11 I/O VCC12 I/O VCC13 I/O VCC14 I/O VCC15 I/O VCC16
Figure 7. MAX13108E Multiplexing Configuration
14 ______________________________________________________________________________________
16-Channel Buffered CMOS Logic-Level Translators MAX13101E/MAX13102E/MAX13103E/MAX13108E
RC 1M CHARGE-CURRENTLIMIT RESISTOR HIGHVOLTAGE DC SOURCE CS 100pF RD 1500 DISCHARGE RESISTANCE STORAGE CAPACITOR DEVICE UNDER TEST IP 100% 90% AMPERES 36.8% 10% 0 0 tRL Ir PEAK-TO-PEAK RINGING (NOT DRAWN TO SCALE)
TIME tDL CURRENT WAVEFORM
Figure 8a. Human Body ESD Test Model
Figure 8b. Human Body Model Current Waveform
ESD Test Conditions
ESD performance depends on a variety of conditions. Contact Maxim for a reliability report that documents test setup, test methodology, and test results.
Applications Information
Power-Supply Decoupling
To reduce ripple and the chance of transmitting incorrect data, bypass VL and VCC to ground with 0.1F capacitors. To ensure full 15kV ESD protection, bypass VCC to ground with a 1F ceramic capacitor. Place all capacitors as close to the power-supply inputs as possible.
Human Body Model
Figure 8a shows the Human Body Model and Figure 8b shows the current waveform it generates when discharged into a low impedance. This model consists of a 100pF capacitor charged to the ESD voltage of interest, which is then discharged into the test device through a 1.5k resistor.
Capacitive Loading
Capacitive loading on the I/O lines impacts the rise time (and fall time) of the MAX13101E/MAX13102E/ MAX13103E/MAX13108E when driving the signal lines. The actual rise time is a function of the parasitic capacitance, the supply voltage, and the drive impedance of the MAX13101E/MAX13102E/MAX13103E/MAX13108E. For proper operation, the signal must reach the VOH as required before the rise-time accelerators turn off.
Machine Model
The Machine Model for ESD tests all pins using a 200pF storage capacitor and zero discharge resistance. Its objective is to emulate the stress caused by contact that occurs with handling and assembly during manufacturing. All pins require this protection during manufacturing, not just inputs and outputs. Therefore, after PC board assembly, the Machine Model is less relevant to I/O ports.
______________________________________________________________________________________
15
16-Channel Buffered CMOS Logic-Level Translators MAX13101E/MAX13102E/MAX13103E/MAX13108E
Ordering Information/Selector Guide (continued)
PART MAX13102EEWX+ MAX13102EETL+ MAX13103EEWX+ MAX13103EETL+ MAX13108EEWX+ MAX13108EETL+ PIN-PACKAGE 36 WLP** 3.06mm x 3.06mm 40 TQFN-EP*** 5mm x 5mm x 0.8mm 36 WLP** 3.06mm x 3.06mm 40 TQFN-EP*** 5mm x 5mm x 0.8mm 36 WLP** 3.06mm x 3.06mm 40 TQFN-EP*** 5mm x 5mm x 0.8mm DATA RATE (Mbps) 20 20 20 20 20 20 I/O VL STATE DURING SHUTDOWN 6k to GND 6k to GND High impedance High impedance High impedance High impedance I/O VCC STATE DURING SHUTDOWN High impedance High impedance High impedance High impedance High impedance High impedance MULTIPLEXER FEATURE No No No No Yes Yes
Note: All devices are specified over the -40C to +85C operating temperature range. +Denotes a lead-free/RoHS-compliant package. **WLP bumps are in a 6 x 6 array. ***EP = Exposed pad.
Pin Configurations (continued)
TOP VIEW OF BOTTOM LEADS
I/O VCC10 I/O VCC11 I/O VCC5 I/O VCC6 I/O VCC7 I/O VCC8 I/O VCC9 GND I/O VCC12 22 GND 21 20 I/O VCC13 19 I/O VCC14 18 I/O VCC15 17 I/O VCC16 16 VCC 15 VL 14 I/O VL16 *EP 13 I/O VL15 12 I/O VL14 11 I/O VL13 2 I/O VL5 3 I/O VL6 4 I/O VL7 5 I/O VL8 6 I/O VL9 7 I/O VL10 8 I/O VL11 9 I/O VL12 10 MULT
30 I/O VCC4 I/O VCC3 I/O VCC2 I/O VCC1 VCC VL I/O VL1 I/O VL2 I/O VL3 I/O VL4 31 32 33 34 35 36 37 38 39 40
29
28
27
26
25
24
23
MA131018E
+
1 GND
* EXPOSED PAD CONNECTED TO GROUND
TQFN
16
______________________________________________________________________________________
16-Channel Buffered CMOS Logic-Level Translators
Pin Configurations (continued)
MAX13101E/MAX13102E/MAX13103E
1 F VCC E I/O VCC1 D I/O VCC2 C I/O VL2 B I/O VL1 A I/O VL4 I/O VL7 I/O VL10 I/O VL13 I/O VL16 A I/O VL5 I/O VL8 I/O VL11 I/O VL14 EN B I/O VL1 I/O VL4 I/O VL7 I/O VL10 I/O VL13 I/O VL16 I/O VCC5 I/O VCC8 I/O VCC11 I/O VCC14 GND C I/O VL2 I/O VL5 I/O VL8 I/O VL11 I/O VL14 MULT I/O VCC4 I/O VCC7 I/O VCC10 I/O VCC13 I/O VCC16 D I/O VCC2 I/O VCC5 I/O VCC8 I/O VCC11 I/O VCC14 GND I/O VCC3 I/O VCC6 I/O VCC9 I/O VCC12 I/O VCC15 E I/O VCC1 I/O VCC4 I/O VCC7 I/O VCC10 I/O VCC13 I/O VCC16 2 3 4 5 6 F VCC I/O VCC3 I/O VCC6 I/O VCC9 I/O VCC12 I/O VCC15 1 2
MAX13101E/MAX13102E/MAX13103E/MAX13108E
MAX13108E
3 4 5 6
+ VL
I/O VL3
I/O VL6
I/O VL9
I/O VL12
I/O VL15
+ VL
I/O VL3
I/O VL6
I/O VL9
I/O VL12
I/O VL15
WLP (BOTTOM VIEW)
WLP (BOTTOM VIEW)
Typical Operating Circuit
PROCESS: BiCMOS
+1.8V +3.3V
Chip Information
Package Information
For the latest package outline information and land patterns, go to www.maxim-ic.com/packages.
VL EN/(MULT) +1.8V SYSTEM CONTROLLER DATA I/O VL_ VCC
PACKAGE TYPE 36 WLP 40 TQFN-EP
PACKAGE CODE W363A3-1 T4055-1
DOCUMENT NO. 21-0024 21-0140
MAX13101E MAX13102E MAX13103E MAX13108E
I/O VCC_
+3.3V SYSTEM
DATA
GND
( ) ARE FOR MAX13108E
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17
16-Channel Buffered CMOS Logic-Level Translators MAX13101E/MAX13102E/MAX13103E/MAX13108E
Revision History
REVISION NUMBER 2 3 REVISION DATE 8/06 6/08 DESCRIPTION Release of the MAX13101EETL+ Changed UCSP to WLP packaging PAGES CHANGED -- 1, 2, 9, 10, 11, 16, 17, 18, 19
Maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim product. No circuit patent licenses are implied. Maxim reserves the right to change the circuitry and specifications without notice at any time.
18 ____________________Maxim Integrated Products, 120 San Gabriel Drive, Sunnyvale, CA 94086 408-737-7600 (c) 2008 Maxim Integrated Products is a registered trademark of Maxim Integrated Products, Inc.

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